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Chip package structure and manufacturing method thereof for effectively lowering manufacturing costs and improving yield and reliability of the chip package structure

机译:芯片封装结构及其制造方法,可有效降低制造成本,提高芯片封装结构的良率和可靠性

摘要

A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire.
机译:芯片封装结构包括电路基板,芯片,至少一条键合线和粘合剂层。电路基板具有一接合面以及设置于该接合面上的至少一焊垫。芯片设置在电路基板的接合表面上,并具有远离电路基板的有源表面和设置在该有源表面上的至少一个接触焊盘。键合线连接在接触垫和垫之间,使得芯片通过键合线电连接到电路基板。键合线包括铜层,覆盖铜层的镍层和覆盖镍层的金层。粘合层设置在焊盘和键合线之间以及接触垫和键合线之间,并且分别覆盖键合线的两个端子。

著录项

  • 公开/公告号US8242594B2

    专利类型

  • 公开/公告日2012-08-14

    原文格式PDF

  • 申请/专利权人 CHUNG-PAN WU;

    申请/专利号US20090542154

  • 发明设计人 CHUNG-PAN WU;

    申请日2009-08-17

  • 分类号H01L23/34;H01L23/48;H01L21/44;

  • 国家 US

  • 入库时间 2022-08-21 17:30:52

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