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Vertical-channel junction field-effect transistors having buried gates and methods of making

机译:具有掩埋栅的垂直沟道结型场效应晶体管及其制造方法

摘要

Semiconductor devices and methods of making the devices are described. The devicescan be implemented in SiC and can include expitaxially grown n-type drift andp-type trenched gate regions, and an n-type epitaxially regrown channel regionon top of the trenched p-gate regions. A source region can be epitaxially regrownon top of the channel region or selectively implanted into the channel region.Ohmic contacts to the source, gate and drain regions can then be formed. The devicescan include edge termination structures such as guard rings, junction terminationextensions (JTE), or other suitable p-n blocking structures. The devices canbe fabricated with different threshold voltages, and can be implemented forboth depletion and enhanced modes of operation for the same channel doping. Thedevices can be used as discrete power transistors and in digital, analog, andmonolithic microwave integrated circuits.
机译:描述了半导体器件及其制造方法。设备可以用SiC实现,并且可以包括外延生长的n型漂移和p型沟槽栅区和n型外延长沟道区在沟槽的p栅极区域的顶部。源区域可以外延再生在沟道区的顶部上或选择性地植入沟道区中。然后可以形成与源极,栅极和漏极区域的欧姆接触。设备可以包括边缘终端结构,例如保护环,结终端扩展(JTE)或其他合适的p-n阻止结构。设备可以用不同的阈值电压制造,并可以实现同一通道掺杂的耗尽和增强工作模式都可以。的器件可用作离散功率晶体管以及数字,模拟和单片微波集成电路。

著录项

  • 公开/公告号AU2005335231B2

    专利类型

  • 公开/公告日2012-07-05

    原文格式PDF

  • 申请/专利权人 MISSISSIPPI STATE UNIVERSITY;SS SC IP LLC;

    申请/专利号AU2005335231B2

  • 发明设计人 CHENG LIN;MAZZOLA MICHAEL S.;

    申请日2005-11-16

  • 分类号H01L29/74;H01L29/80;H01L31/111;H01L31/112;

  • 国家 AU

  • 入库时间 2022-08-21 17:20:00

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