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Vertical-channel junction field-effect transistors having buried gates and methods of making

机译:具有掩埋栅的垂直沟道结型场效应晶体管及其制造方法

摘要

Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.
机译:描述了半导体器件及其制造方法。该器件可以用SiC实现,并且可以包括外延生长的n型漂移区和p型沟槽栅区,以及在沟槽p栅区顶部的n型外延生长沟道区。源极区域可以在沟道区域的顶部上外延生长或选择性地注入到沟道区域中。然后可以形成与源极,栅极和漏极区域的欧姆接触。所述装置可包含边缘终止结构,例如保护环,结终止延伸部(JTE)或其他合适的p-n阻挡结构。可以用不同的阈值电压来制造器件,并且可以针对相同的沟道掺杂将其实现为耗尽和增强操作模式。该器件可用作离散功率晶体管以及数字,模拟和单片微波集成电路。

著录项

  • 公开/公告号EP2442365A3

    专利类型

  • 公开/公告日2013-07-17

    原文格式PDF

  • 申请/专利权人 SS SC IP LLC;MISSISSIPPI STATE UNIVERSITY;

    申请/专利号EP20110189795

  • 发明设计人 MAZZOLA MICHAEL S.;CHENG LIN;

    申请日2005-11-16

  • 分类号H01L29/74;H01L31/111;H01L29/80;H01L31/112;

  • 国家 EP

  • 入库时间 2022-08-21 16:32:44

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