首页> 外国专利> METHOD FOR FABRICATING SUBSTRATELESS SEMICONDUCTOR CHIP PACKAGE AND SUBSTRATELESS SEMICONDUCTOR CHIP PACKAGE FABRICATED USING THEREOF

METHOD FOR FABRICATING SUBSTRATELESS SEMICONDUCTOR CHIP PACKAGE AND SUBSTRATELESS SEMICONDUCTOR CHIP PACKAGE FABRICATED USING THEREOF

机译:一种制造无铅半导体芯片封装的方法以及利用该方法制造的无铅半导体芯片封装的方法

摘要

PURPOSE: A fabricating semiconductor chip package manufacturing method and manufactured fabricating semiconductor chip package using the same are provided to use detachable 3-layered copper foil as a carrier substrate capable of detaching in final step instead of an organic substrate, thereby enabling to prevent a printed circuit substrate bending problem during a package process and possible damage on the semiconductor chip. CONSTITUTION: A first electrode plate layer and circuit layer connected to the first electrode plate layer are formed on the upper part of a carrier substrate. A second electrode plate layer(170) is formed on the upper part of the circuit layer. A circuit bonding pad layer is formed on the upper part of the second electrode plate layer. A semiconductor chip(200) including a die bonding pad layer in the upper part is formed with separation on the upper part of the circuit layer. The die bonding pad layer(220) and circuit bonding pad layer(180) are connected using a bonding wire(190). A package layer(230) protecting the semiconductor chip and circuit layer is formed on the upper part of the carrier substrate. The lower part of the circuit layer is exposed by eliminating the carrier substrate. An insulating layer is formed on the bottom surface of the exposed circuit layer. The lower part of the circuit layer is exposed by eliminating the first electrode plate layer. A surface processing layer(250) is formed on the lower part of the circuit layer(160). A solder ball(260) is formed in the lower part of the surface processing layer.
机译:用途:提供一种制造半导体芯片封装的方法以及使用该制造半导体芯片封装的制造的半导体芯片封装,以使用可分离的三层铜箔作为能够在最后步骤分离的载体基板而不是有机基板,从而能够防止印刷封装过程中电路基板的弯曲问题以及对半导体芯片的可能损坏。组成:第一电极板层和连接到第一电极板层的电路层形成在载体基板的上部。在电路层的上部形成第二电极板层(170)。在第二电极板层的上部上形成电路焊盘层。在电路层的上部上分离地形成在上部包括管芯焊盘层的半导体芯片(200)。芯片键合焊盘层(220)和电路键合焊盘层(180)使用键合线(190)连接。保护半导体芯片和电路层的封装层(230)形成在载体基板的上部上。通过去除载体基板来暴露电路层的下部。绝缘层形成在暴露的电路层的底表面上。通过去除第一电极板层来暴露电路层的下部。在电路层(160)的下部上形成表面处理层(250)。在表面处理层的下部形成有焊球(260)。

著录项

  • 公开/公告号KR101098994B1

    专利类型

  • 公开/公告日2011-12-28

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20100009581

  • 发明设计人 이효수;이규제;권혁천;

    申请日2010-02-02

  • 分类号H01L21/60;

  • 国家 KR

  • 入库时间 2022-08-21 17:10:56

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