VOLTAGE CONTROL METHOD AND A MEMORY DEVICE USING THE SAME CAPABLE OF MINIMIZING A COUPLING NOISE BETWEEN A WRITE GLOBAL BIT LIEN AND A READ GLOBAL BIT LINE

摘要

PURPOSE: A voltage control method and a memory device using the same are provided to increase a writing operation by shortening discharge time of a write global bit line.;CONSTITUTION: A memory cell array includes a plurality of global bit lines, a plurality of sub arrays, and a plurality of local bit line selection circuits. A first sub array(21-1) includes a plurality of nonvolatile memory cells(23). A first local bit line selection circuit(22-1) includes a plurality of switching circuits. A switching circuit connects the plurality of global bit liens to a discharge line in response to a discharge enable signal. A first discharge circuit supplies a first voltage to the discharge line. The first voltage is higher than a ground voltage.;COPYRIGHT KIPO 2012