FLASH MEMORY DEVICE CAPABLE OF REDUCING READ TIME, IN WHICH GLOBAL BIT LINE DISCHARGE IS PERFORMED BEFORE SELECTING A GLOBAL BIT LINE

摘要

PURPOSE: A flash memory device capable of reducing a read time is provided to reduce a data read time in a burst read mode. CONSTITUTION: A semiconductor memory device includes a plurality of first bit lines and a plurality of second bit lines. A signal generator circuit generates a flag signal informing a burst read operation. An address generator circuit(200) generates an address in response to the flag signal. A column selection circuit(120) selects a part of the plurality of first bit lines in response to the address. The selected first bit lines are connected to the plurality of second bit lines respectively. A discharge circuit discharges voltages of the plurality of second bit lines in response to the flag signal.