首页>
外国专利>
SEMICONDUCTOR MP WAFER PROCESS CAPABLE OF REDUCING TIME AND COSTS OF CHECKING AN IC DESIGN WINDOW
SEMICONDUCTOR MP WAFER PROCESS CAPABLE OF REDUCING TIME AND COSTS OF CHECKING AN IC DESIGN WINDOW
展开▼
机译:具有减少IC设计窗口时间和成本的半导体MP晶片工艺
展开▼
页面导航
摘要
著录项
相似文献
摘要
PURPOSE: A semiconductor MP wafer process is provided to reduce manufacturing costs and improve functional integration by connecting heterogeneous semiconductor process technology or mixed-mode IC design.;CONSTITUTION: An MP wafer(100) includes a plurality of MP chips(101). An MP mask set(400) includes a plurality of masks(4A,4B,4C,4D,4E,4F,4F') to form various device components with different levels. IC patterning information includes a semiconductor device source/drain forming pattern, a mutual connection forming pattern or a via hole forming pattern. A link process is a wire bonding process, a mutual connection unit bumping process or a silicon through electrode process.;COPYRIGHT KIPO 2012
展开▼