DEEP N-WELL GUARD RING AND A 3D INTEGRATED CIRCUIT INCLUDING THE SAME CAPABLE OF REDUCING COUPLING NOISE OF A THROUGH SILICON VIA

摘要

PURPOSE: A deep N-well guard ring and a 3D integrated circuit including the same are provided to reduce power noise of the 3D integrated circuit due to high frequency signals by connecting the deep N-well guard ring located around the through silicon via to a power source.;CONSTITUTION: An N-well region(550) is formed on one side of a semiconductor chip and is formed around a through silicon via(510). An N type impurity region(540) is formed on the N-well region. A guard ring electrode is formed on the N type impurity region. A depletion region(560) is formed around the N-well region of the semiconductor chip.;COPYRIGHT KIPO 2012