SIMPLIFICATION DEVICE AND SIMPLIFICATION METHOD FOR LOGIC CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a simplification device and a simplification method for a logic circuit that can minimize the number of gates and the number of signal lines, and also can be made less in number of times of simplification and execution time than any other method.;SOLUTION: There is provided the simplification device for a logic circuit which uses allowability of a fault, and includes: fault place set generation means; first simplification means of selecting from allowable faults in an undecided area among fault places generated by the fault place set generation means, and selecting a fault place in an allowable area after completion of selection of an allowable fault in the undecided area so as to achieve circuit simplification; second simplification means of achieving circuit simplification in the order of fault places where the large number of signal lines can be removed; third simplification means of achieving circuit simplification in the order of fault places where the small number of signal lines can be removed; selection means of selecting simplification means which are large in decrement of the number of gates, the number of signal lines, etc. from among the simplification means; and circuit design modification means of modifying the design of a circuit by one of the selected means.;COPYRIGHT: (C)2013,JPO&INPIT