TEST SIMPLIFICATION LOGIC SYNTHESIS SYSTEM AND TEST SIMPLIFYING CIRCUIT

摘要

PURPOSE: To improve a true fault detection rate in a test using a test pattern by a transition fault model by eliminating a an defined state, in a logic synthesis system in which a circuit can be generated from a state transition description. ;CONSTITUTION: This system is equipped with a non-defined state preventing means 5 which analyzes the state transition description of a synchronous sequential circuit, calculates the number of states (non-defined state) which don't correspond to the states defined in the description which should appear at the time of allocating the states defined in the description to a storage element, defines the states in the equivalent number as the abnormal states, detects the unused output patterns of the description, and adds the description so that the unused output patterns can be assigned as the outputs of the abnormal states.;COPYRIGHT: (C)1994,JPO&Japio