Simplification on Logic Circuits Extracted from Transistor Circuits for Logic Verification Purpose

摘要

Increase in chip complexity has made logic verification tools play a more and more important role in VLSI design. Recently, several logic verification algorithms [2,3,4,5,6] for combinational circuits have been developed. Combining these tools with Tranalyze [1], a tool which can extract the functionally equivalent gate level representation from a switch-level circuit, it is theoretically possible to check the equivalency between a logic circuit and a switch-level circuit. Our experimental results show, though, that directly comparing a logic circuit with the logic circuit extracted by Tranalyze is less effective and even impossible for some logic verification tools. This paper proposes a circuit simplification technique which simplifies circuits extracted by Tranalyze, greatly improving the performance of the logic verification tools.