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SYSTEM AND METHOD FOR MANAGING TIMING MARGIN IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
SYSTEM AND METHOD FOR MANAGING TIMING MARGIN IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
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机译:分层集成电路设计过程中的时序裕量管理系统和方法
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摘要
A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file, (2) receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in the model file, (3) generate block implementation timing constraints employing the at least one timing environment margin and the at least one operational margin and (4) generate a block timing model employing the at least one abstracted view margin and the at least one operational margin.
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