An integrated circuit hierarchical design system for optimizing a circuit locating between flip-flops included in a lower layer through a higher layer among layers forming an integrated circuit, which shifts a layer section as a boundary between the higher layer and the lower layer that locates on the circuit to the vicinity of a connection portion between the flip-flop and the circuit to include the circuit in either the higher layer or lower layer, thereby eliminating the need of distributing propagation delays of the circuit.
展开▼