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Integrated circuit hierarchical design system, integrated circuit hierarchical design program and integrated circuit hierarchical design method

机译:集成电路分层设计系统,集成电路分层设计程序和集成电路分层设计方法

摘要

An integrated circuit hierarchical design system for optimizing a circuit locating between flip-flops included in a lower layer through a higher layer among layers forming an integrated circuit, which shifts a layer section as a boundary between the higher layer and the lower layer that locates on the circuit to the vicinity of a connection portion between the flip-flop and the circuit to include the circuit in either the higher layer or lower layer, thereby eliminating the need of distributing propagation delays of the circuit.
机译:一种集成电路分层设计系统,用于通过形成集成电路的各层中的较高层来优化位于较低层中包括的触发器之间的电路,该电路将层部分作为位于较高层和位于较低层上的较低层之间的边界而移动将该电路连接到触发器和电路之间的连接部分附近,以将该电路包括在较高层或较低层中,从而消除了分配电路的传播延迟的需要。

著录项

  • 公开/公告号US2006006473A1

    专利类型

  • 公开/公告日2006-01-12

    原文格式PDF

  • 申请/专利权人 YUICHI NAKAMURA;

    申请/专利号US20050176211

  • 发明设计人 YUICHI NAKAMURA;

    申请日2005-07-08

  • 分类号H01L29/76;

  • 国家 US

  • 入库时间 2022-08-21 21:46:27

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