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Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET
Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET
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机译:高K金属栅极P型MOSFET的低阈值电压和反型氧化物厚度缩放
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摘要
A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.
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机译:一种形成半导体结构的方法。该半导体结构具有半导体衬底以及设置在该衬底上的nFET和pFET。该pFET具有形成在半导体衬底的表面之上或之内的半导体SiGe沟道区域以及具有在沟道区域之上的氧化物层和在氧化物层之上的高k介电层的栅极电介质。栅电极覆盖栅电介质,并具有与高k层邻接的下部金属层,与下部金属层邻接的清除金属层和与清除金属层邻接的上部金属层。金属层清除了衬底(nFET)和SiGe(pFET)与氧化物层之间的氧气,从而有效降低了pFET的T inv Sub>和V t Sub>,同时缩放Tinv并保持nFET的Vt,导致pFET的V t Sub>值。
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