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SEMICONDUCTOR DEVICE FORMING A HIGH RESISTANT VOLTAGE METAL INSULATOR SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND A RESISTANCE ELEMENT ON THE SAME BOARD AND A MANUFACTURING METHOD THEREOF
SEMICONDUCTOR DEVICE FORMING A HIGH RESISTANT VOLTAGE METAL INSULATOR SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND A RESISTANCE ELEMENT ON THE SAME BOARD AND A MANUFACTURING METHOD THEREOF
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机译:在高电压金属绝缘子上形成半导体器件的半导体器件场效应晶体管及其同一板上的电阻元件及其制造方法
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摘要
PURPOSE: A semiconductor device forming a high resistant voltage metal insulator semiconductor field effect transistor and a resistance element on the same board and a manufacturing method thereof are provided to simultaneously planarizing the surface of a semiconductor substrate and reduce a chip size by reducing a rate of a dummy active region to a total area of the semiconductor substrate.;CONSTITUTION: A element isolation groove(2) is formed on the front side of a semiconductor substrate(1). An n-type buried layer(3) and a p-type buried layer(4) are formed on a deep domain of the semiconductor substrate. An n-type well(5) functions as a source and a drain of a high resistant voltage n-channel type MISFET(metal insulator semiconductor field effect transistor). A P-type well(6) serves as a part of a source and a drain of a high resistant voltage p-channel type MISFET. A gate insulating layer(7) is formed on the surface of the semiconductor substrate. A resistance element(IR) is formed on the upper part of the gate insulating layer.;COPYRIGHT KIPO 2013;[Reference numerals] (AA) 7: gate insulating layer; (BB) IR: resistance element
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