MULTI-LAYER SCAVENGING METAL GATE STACK FOR AN ULTRA-THIN INTERFACIAL DIELECTRIC LAYER CAPABLE OF REDUCING PRODUCTION COSTS

摘要

PURPOSE: A multi-layer scavenging metal gate stack for an ultra-thin interfacial dielectric layer is provided to improve device performance by using a scaling down process.;CONSTITUTION: An interfacial dielectric layer is arranged on a semiconductor substrate(310). A high K dielectric layer is arranged on the interfacial dielectric layer(320). A first conductive layer is arranged on the high K dielectric layer. A second conductive layer is arranged on the first conductive layer. A second metal layer is arranged on the first metal layer(340).;COPYRIGHT KIPO 2013;[Reference numerals] (310) Arranging an interfacial dielectric layer on a semiconductor substrate; (320) Arranging a high K dielectric layer on the interfacial dielectric layer; (330) Arranging a first metal layer on the high K dielectric layer and, wherein the first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer; (340) Arranging a second metal layer on the first metal layer, wherein the second metal layer includes a material that adsorbs the oxygen impurities from any overlaying layers and prevents the oxygen impurities from diffusing into the first metal layer; (350) Arranging a third metal layer on the second metal layer; (360) Arranging a fourth metal layer on the third metal layer;