A capacitor-less dynamic semiconductor memory device and a method of operating the same are provided to prevent the increase of layout area by comprising a shared bit line voltage sense amplifier for a fixed number of bit line pairs of a memory block having a twin cell structure using a floating body transistor. A memory block comprises a twin cell group. The twin cell group comprises a true cell group and an inversion cell group. The true cell group has a floating body having a gate connected to each word line, a first electrode connected to a bit line and a second electrode connected to a first source line, and stores data. The inversion cell group has a floating body having a gate connected to each word line, a second electrode connected to an inverted bit line and a second electrode connected to a second source line, and stores data with opposite phase to the data. A bit line selection part(311_R) and a source line selection part select a bit line pair comprising the bit line and an inverted bit line in response to a bit line selection signal, and apply a voltage to the bit line pair and the source line, and control connection between the bit line pair and a sense bit line pair, and are comprised in the twin cell group. A sense amplification part(331) senses and amplifies voltage difference of the sense bit line pair.
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