首页> 外国专利> METHOD AND APPARATUS OF ADDRESS BUS CODING/DECODING FOR LOW-POWER VERY LARGE SCALE INTEGRATION SYSTEM

METHOD AND APPARATUS OF ADDRESS BUS CODING/DECODING FOR LOW-POWER VERY LARGE SCALE INTEGRATION SYSTEM

机译:低功耗超大规模集成系统的地址总线编码/解码方法和装置

摘要

A method and a device for coding/decoding an address bus in a low-power VLSI system are provided to reduce power consumption by realizing a bit change rate of a bus value lower than a half of total bit number of the bus value. A binary bus value storing part(310) stores the previous bus value. A multi-bit determiner(330) outputs bit information controlling bit inversion by receiving the current bus value, and comparing the bit numbers of '0' and '1'. A bit inverter(350) selectively inverts the current bus value based on the bit information. A vector operator(370) performs vector operation of the selectively inverted current bus value and the previous bus value. An output line adds the bit information controlling the bit inversion to the bit value through vector operation, and outputs the information to the corresponding to bus.
机译:提供一种用于在低功率VLSI系统中对地址总线进行编码/解码的方法和设备,以通过实现总线值的比特变化率低于总线值的总位数的一半来降低功耗。二进制总线值存储部分(310)存储先前的总线值。多位确定器(330)通过接收当前总线值并比较“ 0”和“ 1”的位数来输出控制位反转的位信息。比特反相器(350)基于比特信息选择性地将当前总线值反相。向量运算器(370)对选择性反转的当前总线值和先前的总线值执行向量运算。输出线通过矢量运算将控制位反转的位信息添加到位值,并将该信息输出到对应的总线。

著录项

  • 公开/公告号KR101311617B1

    专利类型

  • 公开/公告日2013-09-26

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20060020164

  • 发明设计人 황상윤;

    申请日2006-03-02

  • 分类号G06F13/38;

  • 国家 KR

  • 入库时间 2022-08-21 16:24:24

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