LAYOUT DESIGNING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN DEVICE

摘要

PROBLEM TO BE SOLVED: To suppress iteration in layout design of a semiconductor integrated circuit to improve a design efficiency.;SOLUTION: A layout design device comprises: a wiring resource calculation part 1 calculating a wiring possible wiring resource in a first area of a semiconductor integrated circuit; a cell arrangement part 2 arranging a plurality of cells on the first area on the basis of the size of the cell; a network connection cost calculation part 3 calculating a network connection cost of the plurality of cells arranged on the first area on the basis of connection information of the cells; a virtual extension area provision part 4 providing a virtual extension area for virtually increasing a size to the cells arranged on the first area, when on the first area the wiring resource is insufficient for the network connection cost; and a cell rearrangement part 5 rearranging the plurality of cells including the cell on the first area, on the basis of the size of the cells increased by the provided virtual extension area.;COPYRIGHT: (C)2014,JPO&INPIT