首页> 外国专利> LAMINATE TYPE NITRIDE SEMICONDUCTOR DEVICE INCLUDING InAlN LAYER AND GaN LAYER

LAMINATE TYPE NITRIDE SEMICONDUCTOR DEVICE INCLUDING InAlN LAYER AND GaN LAYER

机译:包括InAlN层和GaN层的叠层型氮化物半导体器件

摘要

PROBLEM TO BE SOLVED: To solve the problem that when a recess or a partly residual gate electrode is formed in a GaN-based heterojunction lamination structure, dry etching is required and etching damage remains intact in a semiconductor device.;SOLUTION: A source electrode 2 and a drain electrode 6 are formed on the top surface of a GaN-based heterojunction lamination structure, with a recess 8a formed at a position dividing between the source electrode and the drain electrode, and the recess 8a filled with a gate electrode 4. When a GaN-based heterojunction lamination structure where a Ga-containing nitride layer is nonexistent is used for upper layers above the bottom face of the recess 8a, a recess can be formed by wet etching, in which case etching damage does not occur in a Ga-containing nitride layer 10 exposed to the bottom face of the recess 8a. A structure in which a p-type InAlN layer is let partially remain to constitute a gate electrode can also be manufactured by wet etching.;COPYRIGHT: (C)2014,JPO&INPIT
机译:解决的问题:要解决以下问题:当在基于GaN的异质结叠层结构中形成凹槽或部分残留的栅电极时,需要进行干法蚀刻,并且在半导体器件中蚀刻损伤会完好无损。如图2所示,在GaN基异质结层叠结构的上表面上形成有漏电极6,在形成于源电极和漏电极之间的位置处形成有凹部8a,并在该凹部8a中填充有栅电极4。当在凹部8a的底面上方的上层中使用不存在含Ga的氮化物层的GaN类异质结叠层结构时,可以通过湿法蚀刻形成凹部,在这种情况下,不会产生蚀刻损伤。暴露于凹部8a的底面的含Ga的氮化物层10。还可以通过湿蚀刻来制造其中部分保留p型InAlN层以构成栅电极的结构。版权所有:(C)2014,JPO&INPIT

著录项

  • 公开/公告号JP2014056998A

    专利类型

  • 公开/公告日2014-03-27

    原文格式PDF

  • 申请/专利权人 TOYOTA CENTRAL R&D LABS INC;

    申请/专利号JP20120201987

  • 发明设计人 KIGAMI MASAHITO;ISHII EIKO;

    申请日2012-09-13

  • 分类号H01L21/338;H01L29/778;H01L29/812;H01L21/336;H01L29/78;

  • 国家 JP

  • 入库时间 2022-08-21 16:18:23

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号