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METHOD AND SYSTEM FOR A HIGH-DENSITY, LOW-COST, CMOS COMPATIBLE MEMORY
METHOD AND SYSTEM FOR A HIGH-DENSITY, LOW-COST, CMOS COMPATIBLE MEMORY
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机译:高密度,低成本,CMOS兼容存储器的方法和系统
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摘要
Methods and systems for a high-density, low-cost, CMOS compatible memory may comprise a memory cell on a chip, the memory cell comprising: a plurality of capacitor/switch pairs, where for each pair comprising a switch and a capacitor, a source terminal of the switch is coupled to a gate terminal of the capacitor. The memory cell may also comprise a reset transistor, a biasing circuit, and a source follower. A drain terminal of each switch may be coupled to a floating node that couples a source terminal of the reset transistor and a gate terminal of the source follower. Drain and source terminals of each of the switches of the plurality of capacitor/switch pairs may be coupled to ground. A number of the plurality of capacitor/switch pairs may indicate a number of bits in the memory. The biasing circuit may comprise a current mirror. A bit-line for the memory cell may be coupled to a source terminal of the source follower. The bit-line may comprise a metal trace.
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