Metal-Gate MOS Transistor and Method of Forming the Transistor with Reduced Gate-to-Source and Gate-to-Drain Overlap Capacitance

摘要

The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.