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Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width

机译:外延加厚的掺杂或未掺杂核纳米线FET结构和增加有效器件宽度的方法

摘要

Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.
机译:提供了用于增加纳米线FET器件的有效器件宽度的技术。在一个方面,提供了一种制造FET器件的方法。该方法包括以下步骤。提供一种在BOX上具有SOI层的SOI晶片,其中该SOI层存在于掩埋氮化物层和氮化物盖之间。蚀刻SOI层,掩埋的氮化物层和氮化物帽以形成梯形构造的SOI层中的纳米线芯和焊盘。纳米线核心悬挂在BOX上。在纳米线芯的侧壁上方形成外延侧壁。从纳米线芯去除掩埋的氮化物层和氮化物帽。形成栅叠层,该栅叠层围绕每个纳米线芯和外延侧壁的至少一部分。

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