An n-FET with a Si nanowire channel and doped epitaxially-thickened source and drain regions

摘要

Nanowire FETs are typically fabricated with Schottky source and drain contacts [1-2]. More recently doped source and drain contacts obtained by modulated in-situ doping [3] or by masked ion implantation [4] were also achieved. In this report we demonstrate greatly improved on-resistance for grown Si nanowire FETs by using epitaxial doped source and drain and, for the first time, estimate a gate-voltage dependent mobility using combined electrical I{sub}d-V{sub}g measurements and 2-D Poisson-Schrodinger simulations. The main process steps of the device fabrication are shown in Figure 1(a-d). The silicon nanowires were epitaxially grown by the vapor-liquid-solid VLS method in a UHV-CVD chamber, with silane as the silicon precursor and gold as the catalyst. The gold catalyst was etched off and the nanowires were dispensed on a heavily doped host silicon substrate capped by a thin dielectric stack of Si{sub}3N{sub}4 and SiO{sub}2. The host substrate was later used for back-gating the nanowire FETs. A dielectric film of silicon oxide and silicon nitride was blanket deposited over the nanowires, and patterned with contact holes to expose the segments of the nanowire where the source and drain regions were fabricated. The source and drain regions were formed by adding silicon to the exposed nanowire body and implanting it with P. A 1000°C/5 sec rapid thermal anneal was used to activate the implanted dopants. Chemical mechanical polishing (CMP) was applied to electrically isolate the source and drain regions by removing the excess silicon over the silicon nitride. Self-aligned nickel silicide was used to form contacts to the source and drain.