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CONTACT STRUCTURE AND METHOD FOR VARIABLE IMPEDANCE MEMORY ELEMENT

机译:可变阻抗存储元件的接触结构和方法

摘要

A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed.
机译:存储元件可以包括形成在至少一个绝缘层内的开口,该绝缘层形成在暴露于开口底部的第一电极部分和蚀刻停止层的蚀刻停止层上;第二电极部分,形成在开口的至少一个侧面上并与第一电极部分接触,第二电极部分不填充开口并且基本上不形成在至少一个绝缘层的顶表面上;至少一个存储层形成在所述至少一个绝缘层的顶表面上并与第二电极部分接触,所述至少一个存储层可在至少两个阻抗状态之间可逆地编程。还公开了形成这种存储元件的方法。

著录项

  • 公开/公告号EP2691959A4

    专利类型

  • 公开/公告日2014-10-29

    原文格式PDF

  • 申请/专利权人 ADESTO TECHNOLOGIES CORPORATION;

    申请/专利号EP20120791992

  • 发明设计人 GOPALAN CHAKRAVARTHY;

    申请日2012-06-25

  • 分类号H01L45/00;

  • 国家 EP

  • 入库时间 2022-08-21 15:47:01

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