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METHOD AND APPARATUS FOR IMPLEMENTING WRITE LEVELIZATION IN MEMORY SUBSYSTEMS

机译:在存储器子系统中实现写水平的方法和装置

摘要

provides a method and apparatus for aligning clock signals and strobe signals in one set. In one embodiment, the memory controller includes a generator for generating each strobe signal and a clock generator, and each of the strobe signal to generate a clock signal. In addition, the memory controller, a phase restoring engine adapted to receive the error signal from a corresponding memory device further wherein, the error signal is the strobe signal for the clock signal for each of the plurality of cycles of said strobe signal carry the indication of the sort of error. The phase restoration engine includes an accumulator adapted to maintain a cumulative value which depends on the error indication for a plurality of cycles of said strobe signal. Said strobe signal generator is configured to control the delay related to the generation of said strobe signal according to the accumulated value. ;
机译:提供了一种用于在一组中对准时钟信号和选通信号的方法和装置。在一个实施例中,存储控制器包括用于产生每个选通信号的发生器和时钟发生器,以及每个选通信号以产生时钟信号。另外,所述存储器控制器,适于从相应的存储器设备接收所述误差信号的相位恢复引擎,其中,所述误差信号是针对所述选通信号的多个周期中的每个周期的时钟信号的选通信号,所述选通信号携带所述指示。这类错误。相位恢复引擎包括累加器,该累加器适于在所述选通信号的多个周期中维持取决于误差指示的累加值。所述选通信号发生器被配置为根据累加值来控制与所述选通信号的产生有关的延迟。 ;

著录项

  • 公开/公告号KR101443891B1

    专利类型

  • 公开/公告日2014-09-24

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20107029336

  • 发明设计人 시얼스 숀;

    申请日2009-05-27

  • 分类号G06F13/16;

  • 国家 KR

  • 入库时间 2022-08-21 15:40:06

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