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EPITAXIAL WAFER FOR HETEROJUNCTION BIPOLAR TRANSISTORS, AND HETEROJUNCTION BIPOLAR TRANSISTOR ELEMENT
EPITAXIAL WAFER FOR HETEROJUNCTION BIPOLAR TRANSISTORS, AND HETEROJUNCTION BIPOLAR TRANSISTOR ELEMENT
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机译:双结双极晶体管的外延晶片和双结双极晶体管的外延晶片
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摘要
PROBLEM TO BE SOLVED: To provide an epitaxial wafer for heterojunction bipolar transistors and a heterojunction bipolar transistor element which enable the increase in current gain while minimizing a turn-on voltage.;SOLUTION: An epitaxial wafer 100 for heterojunction bipolar transistors comprises: a base layer 105 made of InyGa1-yAs(0y≤0.10); a collector layer 103; an energy barrier-reduction layer 104 made of Inx→0Ga1-x→1As(0x≤0.10), where the composition of In decreases from the base layer 105 toward the collector layer 103, of which the thickness is less than 30 nm; and an emitter layer 106 made of InzGa1-zP(0.48≤z≤0.58). The total layer thickness of the energy barrier-reduction layer 104, the base layer 105, and the emitter layer 106 is 100 nm or less.;COPYRIGHT: (C)2015,JPO&INPIT
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机译:解决的问题:提供用于异质结双极晶体管的外延晶片和异质结双极晶体管元件,其能够在增大电流增益的同时最小化导通电压。解决方案:用于异质结双极晶体管的外延晶片100包括:基极由In y Sub> Ga 1-y Sub> As(0 x→0 Sub> Ga 1-x→1 Sub> As(0 z Sub> Ga 1-z Sub> P(0.48≤z≤0.58)制成的发射极层106。势垒减少层104,基极层105和发射极层106的总层厚为100 nm或更小;版权所有(C)2015,JPO&INPIT
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