首页> 外国专利> NAND ARRAY COMPRISING PARALLEL TRANSISTOR AND TWO-TERMINAL SWITCHING DEVICE

NAND ARRAY COMPRISING PARALLEL TRANSISTOR AND TWO-TERMINAL SWITCHING DEVICE

机译:包括并联晶体管和二端子开关装置的NAND阵列

摘要

Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.
机译:本文描述了提供高性能和效率的NAND架构。举例来说,公开了一种NAND阵列,其包括具有1个晶体管-1双端子存储装置(IT-1D)布置的存储单元。 NAND阵列的存储单元可以从源极到漏极彼此串联地电布置。此外,各个存储单元包括并联连接至两端子存储装置的晶体管组件。在一些实施例中,被激活的晶体管组件的电阻被选择为实质上小于两端子存储器件的电阻,并且被失活的晶体管组件的电阻被选择为实质上高于两端子存储器件。因此,通过激活或去激活晶体管组件,施加到存储单元的信号可以被短路通过双端存储器件,或者分别被引导通过双端存储器件。

著录项

  • 公开/公告号US2015248931A1

    专利类型

  • 公开/公告日2015-09-03

    原文格式PDF

  • 申请/专利权人 CROSSBAR INC.;

    申请/专利号US201414194402

  • 发明设计人 HAGOP NAZARIAN;

    申请日2014-02-28

  • 分类号G11C13;H01L27/24;

  • 国家 US

  • 入库时间 2022-08-21 15:25:31

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