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Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards
Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards
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机译:用于多种无线标准的交织器表高速计算的可编程电路
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摘要
A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.
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