首页> 外国专利> Chip stack device testing method, chip stack device rearranging unit, and chip stack device testing apparatus

Chip stack device testing method, chip stack device rearranging unit, and chip stack device testing apparatus

机译:芯片堆叠装置测试方法,芯片堆叠装置重新布置单元和芯片堆叠装置测试装置

摘要

A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested.
机译:可以以低成本精确且有效地测试具有不同外部尺寸的多个芯片堆叠装置。本发明提供一种芯片堆叠装置测试方法,该芯片堆叠装置测试方法通过在测试单元中堆叠通过切割多个芯片而配置的芯片堆叠装置,所述多个芯片通过对被测试的基板进行切割而分离。使用用于芯片堆叠装置的托盘,该托盘具有与被测试的未切割的基板的形状和外部尺寸相同的形状和外部尺寸,一个或多个芯片堆叠装置被附接并支撑到用于芯片堆叠装置的托盘的粘合剂层上以使芯片对准。具有待切块的未切割衬底的各个芯片的位置的芯片堆叠设备,用于芯片堆叠设备的托盘以与对被测试衬底的测试相似的方式安装在测试单元中,并且各个芯片堆叠设备是经过测试。

著录项

  • 公开/公告号US9097761B2

    专利类型

  • 公开/公告日2015-08-04

    原文格式PDF

  • 申请/专利权人 KATSUO YASUTA;YUJI MIYAGI;

    申请/专利号US201113293354

  • 发明设计人 YUJI MIYAGI;KATSUO YASUTA;

    申请日2011-11-10

  • 分类号G01R31/02;G01R31/28;G01R31/26;

  • 国家 US

  • 入库时间 2022-08-21 15:18:00

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号