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Chip Stack Device Testing Method, Chip Stack Device Rearranging Unit, and Chip Stack Device Testing Apparatus

机译:芯片堆叠装置测试方法,芯片堆叠装置重新布置单元和芯片堆叠装置测试设备

摘要

PROBLEM TO BE SOLVED: To enable accurate, efficient, and low-cost inspection of a multilayer-chip device including chips having different external dimensions.;SOLUTION: There is provided a multilayer-chip device inspection method for inspecting a multilayer-chip device configured by laminating a plurality of chips, which are diced and divided from an inspection-target substrate which has been inspected by inspection equipment. Each multilayer-chip device is inspected in such a way that: on an adhesive layer of a multilayer-chip device tray having the same shape and external dimension as the inspection-target substrate before dicing, one or more of the multilayer-chip devices are aligned with and adhesively supported at the positions where the respective chips were in the inspection-target substrate before dicing, and the multilayer-chip device tray is set on the inspection equipment in the same manner as in the inspection of the inspection-target substrate to carry out inspection.;COPYRIGHT: (C)2012,JPO&INPIT
机译:解决的问题:为了能够对包括具有不同外部尺寸的芯片的多层芯片装置进行精确,高效和低成本的检查;解决方案:提供了一种用于检查配置的多层芯片装置的多层芯片装置检查方法。通过层叠多个芯片,将这些芯片从已经由检查设备进行检查的检查目标基板切块并分割。以如下方式检查每个多层芯片装置:在切割之前,在具有与检查对象基板相同的形状和外部尺寸的多层芯片装置托盘的粘合层上,层叠一个或多个多层芯片装置。在切割之前,将各芯片对准并粘附在切割对象基板中的各个位置上,并以与检查对象基板的检查相同的方式将多层芯片装置托盘放置在检查设备上。进行检查;版权所有:(C)2012,JPO&INPIT

著录项

  • 公开/公告号KR101266150B1

    专利类型

  • 公开/公告日2013-05-21

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20110114303

  • 发明设计人 야스타 카츠오;미야기 유지;

    申请日2011-11-04

  • 分类号G01R31/26;H01L21/66;

  • 国家 KR

  • 入库时间 2022-08-21 16:25:11

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