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SYMMETRIC AND ISOLATED LDMOS COMPONENT AND MANUFACTURING METHOD THEREFOR

机译:对称隔离的LDMOS元件及其制造方法

摘要

A symmetric and isolated LDMOS component and a manufacturing method therefor. The symmetric and isolated LDMOS component (1) comprises: a buried-layer isolated-layer (2); a P-type well region (3); a side surface isolated region (4, 5); a gate (6); a source region (7), disposed on one side of the gate (6); a drain region (8), disposed one the other side of the gate (6) and symmetric to the source region (7). The source region (7) and the drain region (8) separately comprise an N-type doped region (74a, 84a) disposed in the P-type well region (3); an N-type drift region (72a, 72b, 82a, 82b) neighboring to the N-type doped region (74a, 84a); a field oxide layer (73a, 73b, 83a, 83b) disposed in the N-type drift region (72a, 72b, 82a, 82b); and a heavily doped N-type region (71a, 81a) disposed on the N-type doped region (74a, 84a). In the P-type well region (3), a P-type injection region (9) is formed between the N-type doped region (74a, 84a) and the buried-layer isolated-layer (2) by means of P-type injection, and the density of an impurity injection surface in the P-type injection is at the magnitude ranging from 1013cm-2 to 1014cm-2.
机译:对称且隔离的LDMOS组件及其制造方法。对称且隔离的LDMOS组件(1)包括:埋层隔离层(2);和P型阱区(3);侧面隔离区域(4、5);一扇门(6);源极区(7),设置在栅极(6)的一侧;漏极区(8)布置在栅极(6)的另一侧并且与源极区(7)对称。源极区域(7)和漏极区域(8)分别包括设置在P型阱区域(3)中的N型掺杂区域(74a,84a);与N型掺杂区(74a,84a)相邻的N型漂移区(72a,72b,82a,82b);设置在N型漂移区(72a,72b,82a,82b)中的场氧化物层(73a,73b,83a,83b);设置在N型掺杂区域(74a,84a)上的重掺杂的N型区域(71a,81a)。在P型阱区域(3)中,通过P-形成在N型掺杂区域(74a,84a)与埋层隔离层(2)之间的P型注入区域(9)。 P型注入,杂质注入表面的密度在10 13 cm -2 到10 14 cm -2

著录项

  • 公开/公告号WO2015103912A1

    专利类型

  • 公开/公告日2015-07-16

    原文格式PDF

  • 申请/专利权人 CSMC TECHNOLOGIES FAB2 CO. LTD.;

    申请/专利号WO2014CN93170

  • 发明设计人 MA DONG;

    申请日2014-12-05

  • 分类号H01L29/78;H01L21/336;

  • 国家 WO

  • 入库时间 2022-08-21 15:05:27

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