Clocked comparator to a bipolar differential amplifier

摘要

The increase in the clock rates clocked comparators to a bipolar differential amplifier (and, for example, this design a / d - converter) has been done essentially owing to improvements in the action of the amplification of the differential amplifier contained in its conductive state. Furthermore, the maximum clock rate, however, limited by the period of time, which, in accordance with a switching of the clock - initially for the degradation of the resulting potential barrier in the currentless state via the base - emitter - pn - transition of the now current-carrying transistors is necessary, i.e. the time for the activation of the respective differential amplifier. The invention is intended to reduce this period of time and thus the clock rate increased further, wherein the known for this purpose, further projections are to be possible,The existing differential amplifier (212, 213), with an additional current source (226), which prevents the latter in the respective timing pauses is without current. The resulting error current of the amplifier is connected in parallel at the input side by a similar amplifier (242, 243) with an inverse to the load inputs (281, 282) switched outputs and a further current sources (227) is compensated for, so that at the output of the clocked comparator (207, 208) by the additional current only a symmetrical and constant offset is caused.According to the invention, the additional components are affixed to the drawing are framed by a dashed line.