Circuit for clock controlled voltage comparator - consists of FETs forming differential amplifier with gate terminals, with FET source and drain terminals coupled in specified manner

摘要

Two FETs (T1, T2) form a self-commutating differential amplifier in which each transistor gate is connected to an input terminal (E1, E2), the source terminals are interconnected and coupled to the drain terminal of a current source FET (T17) whose gate terminal is at a given potential (N5) and the source terminal is earthed. The drain terminals are each connected to source terminals of a self-commutating amplifier FETs (T3, T4). The second amplifier gate terminals are interconnected and coupled to an operational volt. source (+UB1). The drain terminal are each connected to the source terminals of load FETs (T5, T6), forming an operational resistor. The load FET drain terminals are linked to the operational volt. source, their source and gate terminals being linked to self-blocking load FETs (T7, T8). The circuit is completed by a number of output FETs (T13, T14), coupled in specified manner to flip-flop FETs (T9, T10).