An analysis of clock feedthrough noise in bipolar comparators

摘要

The clock feedthrough noise in bipolar comparators using ECL (emitter coupled logic) flip-flops was analyzed. It was found that there were two major sources of intrinsic noise at the input differential stage of a comparator. The first is the base current spike generated by the switching of emitter current at the bipolar latch. The second arises due to the bandpass characteristics of the differential stage. The noise acts like a dynamic offset voltage of the input stage because the two input source resistances, one for V/sub in/ and the other for V/sub ref/, are not fully matched. The authors propose a novel method to determine the bias current level of the input buffers to reduce this offset voltage.