TECHNIQUES FOR IMPROVING GATE CONTROL OVER TRANSISTOR CHANNEL BY INCREASING EFFECTIVE GATE LENGTH

摘要

Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (L_eff) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (X_ud) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (L_eff) and improves the control that the gate has over the channel.