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Inducing localized strain in vertical nanowire transistors
Inducing localized strain in vertical nanowire transistors
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机译:在垂直纳米线晶体管中感应局部应变
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摘要
A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain region, a channel region over the bottom source/drain region, and a top source/drain region over the channel region. A top Inter-Layer Dielectric (ILD) encircles the top source/drain region. The device further includes a bottom ILD encircling the bottom source/drain region, a gate electrode encircling the channel region, and a strain-applying layer having vertical portions on opposite sides of, and contacting opposite sidewalls of, the top ILD, the bottom ILD, and the gate electrode.
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