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DEFECT REDUCTION IN III-V SEMICONDUCTOR EPITAXY THROUGH CAPPED HIGH TEMPERATURE ANNEALING
DEFECT REDUCTION IN III-V SEMICONDUCTOR EPITAXY THROUGH CAPPED HIGH TEMPERATURE ANNEALING
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机译:通过高温退火在III-V型半导体表位中的缺陷减少
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摘要
A structure and method for reducing defects within a III-V compound semiconductor layer grown epitaxially on a mismatched crystalline substrate is provided. The III-V compound semiconductor layer may be surrounded by a thermally stable layer on its sides and a thermally stable capping layer on its upper surface. Subsequent to epitaxial growth, the III-V compound semiconductor layer may be subjected to high temperature annealing in a pressurized atmosphere of the corresponding Group V material present in the III-V compound semiconductor layer. The thermally stable layer and the capping layer may prevent the evaporation of the Group V material from the III-V compound semiconductor layer, as well as cure and rearrange the crystalline lattice structure of the III-V compound semiconductor layer thereby reducing defect density.
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