首页> 外国专利> SINGLE SOURCE/DRAIN EPITAXY FOR CO-INTEGRATING NFET SEMICONDUCTOR FINS AND PFET SEMICONDUCTOR FINS

SINGLE SOURCE/DRAIN EPITAXY FOR CO-INTEGRATING NFET SEMICONDUCTOR FINS AND PFET SEMICONDUCTOR FINS

机译:用于共集成NFET半导体鳍和PFET半导体鳍的单源极/漏极表彰

摘要

A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein.
机译:跨着从半导体衬底的表面向上延伸的nFET半导体鳍片和pFET半导体鳍片形成多个栅极结构。从不受栅极结构保护的nFET半导体鳍和pFET半导体鳍的暴露表面外延生长硼掺杂的硅锗合金材料。然后执行退火。在退火期间,来自硼掺杂的硅锗合金材料的硅和锗扩散到nFET半导体鳍片中,并作为n型掺杂剂在nFET半导体鳍片中形成结。由于硼是IIIA族元素,因此没有任何不利影响。在相同的退火期间,来自掺硼的硅锗合金材料的硼将扩散到pFET半导体鳍中,从而在其中形成结。

著录项

  • 公开/公告号US2016093618A1

    专利类型

  • 公开/公告日2016-03-31

    原文格式PDF

  • 申请/专利权人 INTERNATIONAL BUSINESS MACHINES CORPORATION;

    申请/专利号US201414496815

  • 发明设计人 HEMANTH JAGANNATHAN;ALEXANDER REZNICEK;

    申请日2014-09-25

  • 分类号H01L27/092;H01L29/161;H01L29/167;H01L29/66;H01L21/8258;H01L21/8238;H01L21/225;H01L21/324;H01L29/06;H01L29/20;

  • 国家 US

  • 入库时间 2022-08-21 14:33:39

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