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Coverage enhancement and power aware clock system for structural delay-fault test
Coverage enhancement and power aware clock system for structural delay-fault test
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机译:用于结构延迟故障测试的覆盖范围增强和功率感知时钟系统
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摘要
Methods and devices applying to a clock system of scan circuits to enhance the test coverage for structural delay-fault tests are provided. According to an aspect, a method applying to a clock system of a scan circuit of a scan test containing one or more clock gating cells includes at any stage of the scan test outputting a controllable waveform of a clock signal at each clock gating cell, and eliminating a partially enabled clock signal during a capture cycle at each clock gating cell.
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