OVERLAY FEATURE DESIGN AND METHOD FOR APPLICATION IN WAFER FABRICATION

摘要

The present invention provides a design of overlay feature for wafer fabrication. The design pattern is overlay featuring first via [20] and second via [24] reticles with smaller via boxes instead of one big via box. This way, during application procedures residues can be eliminated after tungsten plug process ensuring new and clean box in box pattern instead of deformed box in box. This overlay feature consist of a four line series of via, via boxes of nine units or more in a line, to eliminate residue after tungsten plug process. This overlay feature consist of a set of four line series of via forming part of a hypothetical square as a replacement of one big square via hole. This design improves the overlay feature and helps overcome overlay measurement problems. As such, improvement in accuracy of data measurement provides correct alignments results which enable alignment correction and thus ensure higher production yield. This design solves the overlay problem and can be placed at any via masks (first via [20] and second via [22]) of new products, replacing standard overlay box-box feature without any changes in process recipes of standard CMOS wafer fabrication.