MTJ MEMORY ARRAY SUBGROUPING METHOD AND RELATED DRIVE CIRCUITRY

摘要

Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.