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Al-poor barrier for InGaAs semiconductor structure

机译:InGaAs半导体结构的贫铝势垒

摘要

The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.
机译:本公开涉及一种半导体结构和制备方法,其包括单晶硅衬底和与该单晶硅衬底邻接的III-V结构。半导体结构包括覆盖III-V结构的In a Ga b As结构,其中a为0.40至1,b为0至0.60,a + b等于1.00。 III-V结构具有背离硅衬底的顶表面。顶面是Ga g X x P p Sb s Z z ,其中X包括Ga以外的一种或多种III族元素,Z是P或Sb以外的一种或多种V族元素。 g为0.80至1.00,x为0至0.20,z为0至0.30,p为0.10至0.55,s为0.50至0.80,g + x等于1.00并且p + s + z为等于1.00。

著录项

  • 公开/公告号US2017054021A1

    专利类型

  • 公开/公告日2017-02-23

    原文格式PDF

  • 申请/专利权人 IMEC VZW;

    申请/专利号US201615208783

  • 发明设计人 BERNARDETTE KUNERT;ROBERT LANGER;

    申请日2016-07-13

  • 分类号H01L29/78;H01L29/06;H01L29/423;H01L29/04;H01L29/205;

  • 国家 US

  • 入库时间 2022-08-21 13:49:38

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