HIGH PERFORMANCE MEMORY BASED PARALLEL AND PIPELINED DWT VLSI ARCHITECTURE

摘要

The discrete wavelet transform (DWT) has been widely used in signal processing and image processing applications because of its ability to decompose a signal at multiple resolution level. As DWT involves intensive computations, the design of efficient VLSI architecture for DWT has become essential, especially for real-time and high speed data processing applications. The design and implementation of efficient high performance DWT VLSI architecture is considered as a challenging task. A near optimum low- complexity DWT architecture based on look up table (LUT) realization is presented in this article. The architecture uses reconfigurable memory based LUT multiplier using computation sharing multipliers (CSHM) and binary based common sub expression elimination (BCSE) in order to exploit high-level of concurrency by means of pipelining and parallel processing. The proposed DWT architecture reduce the area and operate at high speed. The proposed architecture has been implemented and tested on a Virtex-4 vlxl5sf363-12 field-programmable gate array (FPGA). The proposed novel 2-D DWT architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable DWT implementations.