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Parallel/pipeline VLSI architecture for a low-delay CELP coder/decoder
Parallel/pipeline VLSI architecture for a low-delay CELP coder/decoder
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机译:低延迟CELP编码器/解码器的并行/流水线VLSI架构
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摘要
An integrated circuit for processing a speech signal in accordance with a CELP standard includes a plurality of processing elements coupled to a data bus in parallel. Each processing element includes a multiplier and an accumulator. The integrated circuit further includes an auxiliary processing element, which is also coupled to the data bus and has a division unit and a comparator. The plurality of processing elements and the auxiliary processing element are also coupled in a pipeline formation.
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