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A Low Power Celp Decoder VLSI Architecture With Reduced Memory Requirement For Low Bit Rate Speech Codec

机译：低功耗Celp解码器VLSI架构，降低了对低比特率语音编解码器的内存需求

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《》|2001年|P.214-215|共2页
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An-Nan Suen; Jhing-Fa Wang;
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中图分类无线电电子学、电信技术;
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专利

1. A Low-Power DSP Core Architecture for Low Bitrate Speech Codec [J] . Hiroyuki OKUHATA, Morgan H. MIKI, Takao ONOYE IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 1998,第8期

机译：用于低比特率语音编解码器的低功耗DSP内核架构
2. Architectural strategies for low-power VLSI turbo decoders [J] . Masera G., Mazza M., Piccinini G., IEEE transactions on very large scale integration (VLSI) systems . 2002,第3期

机译：低功耗VLSI Turbo解码器的架构策略
3. Architectural strategies for low-power VLSI turbo decoders [J] . Masera G., Mazza M., Piccinini G., IEEE transactions on very large scale integration (VLSI) systems . 2002,第3期

机译：低功耗VLSI Turbo解码器的架构策略
4. A Low Power Celp Decoder VLSI Architecture With Reduced Memory Requirement For Low Bit Rate Speech Codec [C] . An-Nan Suen, Jhing-Fa Wang, Institute of Electric and Electronic Engineer International Conference on Consumer Electronics . 2001

机译：低功耗CELP解码器VLSI架构，具有降低的低位速率语音编解码器的内存要求
5. Objective speech intelligibility assessment using speech recognition and bigram statistics with application to low bit-rate codec evaluation [D] . Teng, Yan 2006

机译：使用语音识别和双字母组统计的客观语音清晰度评估及其在低比特率编解码器评估中的应用
6. A Biomimetic Adaptive Algorithm and Low-Power Architecture for Implantable Neural Decoders [O] . Benjamin I. Rapoport, Woradorn Wattanapanitch, Hector L. Penagos, -1

机译：植入式神经解码器的仿生自适应算法和低功耗架构
7. Architectural Strategies for Low-Power VLSI Turbo Decoders [O] . Guido Masera, Marco Mazza, Gianluca Piccinini, 2002

机译：低功耗VLSI Turbo解码器的架构策略

A Low Power Celp Decoder VLSI Architecture With Reduced Memory Requirement For Low Bit Rate Speech Codec

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