Dynamic random-access memory with embedded artificial neural network functionality

摘要

A highly configurable, extremely dense, high speed and low power artificial neural network is presented. The architecture may utilize DRAM cells for their density and high endurance to store weight and bias values. A number of primary sense amplifiers along with column select lines (CSLs), local data lines (LDLs), and sense circuitry may comprise a single neuron. Since the data in the primary sense amplifiers can be updated with a new row activation, the same hardware can be reused for many different neurons. The result is a large amount of neurons that can be connected by the user. Training can be done in hardware by actively varying weights and monitoring cost. The network can be run and trained at high speed since processing and/or data transfer that needs to be performed can be minimized.