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Detecting circuit design flaws based on timing analysis

机译:基于时序分析检测电路设计缺陷

摘要

An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.
机译:可以分析用于电子电路设计的终点报告。加载静态时序分析运行的结果,从加载的结果中选择路径,并提供特定于技术的上下文数据。另外,针对设计质量参数的所选路径的每个测试点进行确定,以确定设计问题区域,并且通过分析设计问题区域数据与相关因素进行比较,针对每个设计问题区域确定根本原因。一些特定于技术的上下文数据。

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