Multi-rate Iterated Timing Analysis-Based Incremental Circuit Simulation Considering Global Design Changes

摘要

Circuit level incremental simulation is an alternative strategy not only to reduce the circuit simulation time but also to maintain the simulation accuracy. This paper investigates the incremental simulation using the well-known ITA (Iterated Timing Analysis) algorithm for large-scale MOSFET circuits. The global design change has been considered. Also, a new incremental simulation strategy is presented. All proposed methods have been implemented and tested to justify their advantages.