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LOGIC CIRCUIT DESIGN SIMULATION SYSTEM AND LOGIC CIRCUIT SMALL INCREMENT SIMULATION METHOD

机译:逻辑电路设计仿真系统和逻辑电路小增量仿真方法

摘要

PURPOSE: To simulate an electric logic design at a high speed by selectively simulating a part of a design. CONSTITUTION: Logic circuit design entry devices 10A and 10B, a data table generator 12 which generates a design element data table and a network list connection data table, and a model reference library 4 where integrated circuit models are stored are included. Further, a model reference index device 2 which is connected to the data table generator 12 to select a memory pointer to integrated circuit models, a simulation device 14 which receives an output 13 of the data table generator 12, and a test signal input device 20 which inputs a test signal to the simulation device 14 are included. Integrated circuit models and network list data are processed so as to generate simulation data. Thus, the electric logic design is simulated at a high speed.
机译:目的:通过选择性地模拟设计的一部分来高速模拟电气逻辑设计。组成:逻辑电路设计输入设备10A和10B,数据表生成器12,其生成设计元素数据表和网络列表连接数据表,以及模型参考库4,其中存储了集成电路模型。此外,连接到数据表生成器12以选择指向集成电路模型的存储器指针的模型参考索引设备2,接收数据表生成器12的输出13的仿真设备14以及测试信号输入设备20包括将测试信号输入到模拟装置14的装置。处理集成电路模型和网络列表数据以生成仿真数据。因此,可以高速模拟电气逻辑设计。

著录项

  • 公开/公告号JPH03116383A

    专利类型

  • 公开/公告日1991-05-17

    原文格式PDF

  • 申请/专利权人 SUTANREI EMU HAIDEYUUKU;

    申请/专利号JP19900165489

  • 发明设计人 SUTANREI EMU HAIDEYUUKU;

    申请日1990-06-21

  • 分类号G06F11/25;G01R31/3183;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 06:05:59

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